CIE – Components in Electronics

ALINT-PRO adds new mixed-language design rules for more predictable cross-language integration

Aldec, Inc., a specialist in mixed HDL language simulation and verification solutions for FPGA and ASIC designs, has ...
IEEE

VHDL simulation and modeling of an all-digital RF transmitter

Abstract: We describe a simulation technique that uses an event-driven VHDL simulator to model an RF wireless transmitter. The technique is well suited to investigate complex interactions in large SoC ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
GitHub

Chronometer for FPGA chip

counter memory : store the current value of the timer display with 7-segment display command circuit : managing the two buttons as a real professional chronometer (with start, pause, turn counter) ...
IEEE

High-Level Synthesis for FPGAs—A Hardware Engineer’s Perspective

Abstract: The recent decades have witnessed unprecedented advances in the complexity of digital hardware systems, yet their design methods are still mostly based on manual register-transfer level ...
archive

The student's guide to VHDL

Ask the publishers to restore access to 500,000+ books. An icon used to represent a menu that can be toggled by interacting with this icon. A line drawing of the Internet Archive headquarters building ...
GitHub

A VHDL parser for syntax highlighting.

Neovim, using nvim-treesitter and a Tokyo Night colour scheme: Neovim, using nvim-treesitter and a One Dark colour scheme: If you'd like your favourite colour scheme to be listed here, issue a PR with ...